1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the generation of an address offset in response to an address offset generating instruction.
2. Description of the Prior Art
It is known to provide data processing systems of the form illustrated in FIG. 1 of the accompanying drawings. This data processing system comprises a processor core including a register bank 4, a multiplier 6, a shifter 8, an adder 10, an instruction pipeline 12 and an instruction decoder 14. It will be understood by those skilled in this technical field that the processor core 2 will typically include many further circuit elements, which have been omitted from FIG. 1 for the sake of clarity. In operation, the processor core 2 fetches program instructions to the instruction pipeline 12 wherein they are decoded by the instruction decoder 14 to generate control signals that act upon the register bank 4, the multiplier 6, the shifter 8 and the adder 10 as well as other circuit elements to control the desired data processing operations as specified by the program instruction being decoded. The processor core 2 is provided with a data bus, an address bus and an instruction bus.
One type of processing operation that can be required is the generation of an address offset value. One example of this type of operation is the BL/BLX instruction which is present in the Thumb mode of operation of Thumb enabled processors produced by ARM Limited of Cambridge, England. FIG. 2 of the accompanying drawings schematically illustrates such instructions. It will be seen that these instructions can be considered as two 16-bit instructions or one 32-bit instruction. The leading five bits (namely 11110) are decoded as indicating that a BL/BLX instruction is present with the remaining eleven bits within the first two bytes being an offset value, including a leading sign bit S, this being offset field 2. This offset value is then followed by a bit pattern 111t1 and a further eleven bits of offset, this being offset field 1. The “t” bit indicates to the instruction decoder 14 whether the instruction is a BL instruction or a BLX instruction. A BL instruction is a branch with link staying within the Thumb mode of operation. A BLX instruction is a branch with link combined with a switch to the ARM mode of operation.
It will be appreciated that the offset values illustrated in FIG. 2 provide twenty two bits. This offset value is sign-extended as required and then added to the branch instruction's address. This offset value range is able to support branch jumps of plus or minus 4 MB to 16-bit halfword-aligned targets.
As application programs increase in complexity, they also tend to increase in size. It is desirable that it should be possible to make an end-to-end branch within a program image if this is required. Accordingly, as application images are becoming larger and greater in size than 4 MB, a problem arises in that the address offset values which are supported in the instructions have an insufficient range.
FIG. 3 schematically illustrates the action of a BL instruction in jumping the program execution flow to a new point. The maximum jump that can be commanded is constrained by the maximum address offset value which may be specified.
A further problem which should be addressed is the need to provide backwards compatibility in any modified form of the instruction. Thus, whilst adopting completely new instruction encodings for the BL/BLX instead of the old encodings might overcome the address offset range problem, it would suffer from the disadvantage of a lack of backwards compatibility with the existing software written using the legacy instructions. Alternatively, adding new encodings in addition to the existing encodings would be disadvantageously wasteful of instruction encoding bit space.